1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, in particular, a method of manufacturing a driver circuit integral type liquid crystal display LCD in which a thin film transistor TFT using a polycrystal semiconductor layer is formed at a display section and a frame section.
2. Description of the Related Art
Attempts have been made to use the technology of forming a semiconductor film on a substrate in order to enhance integration of an integrated circuit and realize great capacity. Attempts have also been made to mass produce an active matrix type LCD enabling the display of a high resolution and animation image by using a TFT as a switching element of a matrix picture element section on one side of a pair of substrates between which liquid crystal is sandwiched.
In particular, if a TFT having characteristics similar to a MOSFET produced on a silicon substrate can be formed on an insulating substrate, it will be possible to make an integral peripheral driver circuit for supplying a desired driving signal voltage to the matrix picture element section by forming a CMOS on the frame of the substrate, and not only the switching element of the LCD's matrix picture element section. In this way, mass production of an LCD with integrated driver circuit can be achieved.
As an LCD with integrated driver circuit does not require connection of a driver IC to a liquid crystal panel, manufacturing may be simplified and the frame of the device can be miniaturized. In particular, miniaturization of the frame enables miniaturization of the commodity used above LCD module as a monitor in applications such as portable information terminals, handhold video cameras, or the like.
By using a polycrystal semiconductor, in which a large number of monocrystal grains having grain diameter of several hundreds to several thousands of .ANG. exist such that they are in contact as material for a channel layer, such a TFT can become a high speed element applicable to a driver section. In particular, polycrystal silicon, namely, polysilicone (p-Si), can result in mobility of approximately several tens to several hundreds of cm.sup.2 /V.multidot.s. This mobility is two digits larger than that of amorphous silicon (a-Si). Therefore, by forming an N-chTFT and a P-chTFT, a CMOS which has an adequate speed as a driver of LCD is formed.
The applicant of the present invention has developed a method of limiting the processing temperature to below approximately 600.degree. C. This enables rationalizing costs and enables the use of cheap substrates with low heat resistance, such as non-alkali glass substrates or the like. Such a p-SiTFTLCD manufacturing process, one in which the temperature of the complete process is restrained below the heat resistance temperature of the substrate is known as a low temperature process.
In FIG. 1, a section of such a p-Si TFT is shown. On the left side of the drawing, an N-ch TFT is shown, whereas the right side shows a P-ch TFT. On a substrate 50, a gate electrode 51 which is composed of metal such as Cr is formed. A gate insulating film 52 composed of SiNx and/or SiO.sub.2 is further formed in such a manner that the gate insulating film 52 covers the gate electrode 51. On the gate insulating film 52, a p-Si film 53 is formed and, an implantation stopper 54, such as SiO.sub.2, patterned on the shape of the gate electrode 51, is then formed on the p-Si film 53. By utilizing the implantation stopper 54, two lightly doped regions LDs which contain lightly doped N type impurities (N-) and a source region S and a drain region D both of which are arranged outside of the LDs and contain heavily doped N type impurities (N+), respectively, are formed on the N-ch side of the p-Si film 53. On the other hand, similarly on the P-ch side of the p-Si film 53, a source region [S] and a drain region [D] which contain heavily doped P type impurities [P+] are formed. Channel regions CHs are formed on the both sides of the N-ch and the P-ch, just under the implantation stoppers 54 . These CHs are intrinsic layers which do not substantially contain impurities. Interlayer insulating films 55 composed of SiNx are formed in such a manner that they cover the p-Si films 53. On the interlayer insulating films 55, a source electrode 56 and a drain electrode 57 which are composed of metal are formed. These electrodes are connected with the source region [S] and the drain region [D] via contact holes which are made in the respective interlayer insulating films 55. Here, in the picture element section, a pixel electrode for driving liquid crystal composed of a transparent conductive film, such as indium tin oxide ITO, further is formed on the interlayer insulating film which covers the source electrode 56 and the drain electrode 57. The pixel electrode is connected with the source electrode 56.
Such constitution that an intervening LD is formed between the channel region and the source and drain regions S. D. as shown in the N-ch is known as a lightly doped drain LDD. Such LDD constitution is adopted in the LCD for the purpose of suppression of OFF-state current.
Further, it is also acceptable to be a channel doped type TFT which have doped channel regions on the N-ch and P-ch by doping impurities of which conductivity types are opposed to that of the source and drain regions before doping the impurities to the p-Si film 53 as described above.
Such a TFT may be manufactured in the following manner. First, just after forming the gate electrode 51 by sputtering and etching of Cr, SiNx, and SiO.sub.2, which will be the gate insulating film 52, and the a-Si film are consecutively formed by a plasma CVD process without breaking a vacuum. Then, by applying laser annealing to the a-Si film for polycrystallization, the p-Si film 53 is formed. After the SiO.sub.2 is formed on the p-Si film 53, positive type resist is formed on the SiO.sub.2. The resist is then exposed to light through back-exposure such that light is radiated to the resist from the substrate 50 side, reversing the pattern shape of the gate electrode 51. The resist is developed in one step and then the implantation stopper 54 is formed in the same shape as that of the gate electrode 51 by etching an insulating film using the resist as a mask. An N type conductive impurity ion, such as phosphorus P, is then lightly doped using the implantation stopper 54 (resist) as a mask, and the channel region CH, which is just under the implantation stopper, and the LDs, which are on the both sides of the channel region, are formed. The resist is then formed in a shape larger than that of the implantation stopper 54. By heavily doping the N type impurity ion using the resist as a mask, the source region S and the drain region D are formed. Thus, on the N-ch side, the LDD constitution in which the LDs intervene between the channel region CH and the source and drain regions S and D is completed.
With regard to the P-ch side, by similarly reflecting the configuration of the gate electrode 51, the source and drain regions S and D in which P type impurities are heavily doped are formed outside the channel region CH. However, on the P-ch side, the LDD constitution is not adopted.
Next, the interlayer insulating films 55 which cover the N-ch and P-ch TFTs are formed. The contact holes CT are made, a metal film such as Al or Al and Mo is formed, and the source and drain electrodes 56 and 57 are formed by etching. These electrodes are connected to the source region S and the drain region D via contact holes CT, respectively.
The p-Si film is formed by laser annealing to the a-Si film, and, before this annealing step, the vacuum atmosphere of the a-Si film forming step, is broken. At this time, impurities, such as Na adsorb on the surface of the a-Si film or the p-Si film. If these impurity ions are taken into devices, they will cause flat-band voltage to change as moving ions, thereby changing a threshold value. Further, since the p-Si film 53 and the gate insulating film 52 which is a layer under the p-Si film 53 are consecutively formed by the CVD process, a lattice condition of the interface between the gate insulting film 52 and the p-Si film 53 is comparatively good. However, since the top surface of the p-Si film 53 is exposed after forming the a-Si film, there is a lattice defect and the density of the interface state is high. These numerous interface states become traps by producing energy levels in a band gap, thereby taking in electrons from a conduction band and emitting them to a valence band, and drawing electrons in the valence band and then sending them to the conduction band. This causes a problem of lowering an ON-OFF ratio.